The DSP Builder advanced blockset consists of a number of Simulink libraries that
allow you to implement DSP designs quickly and easily. The blockset is based on a
high-level synthesis technology that optimizes the untimed netlist into low-level,
pipelined hardware for the target FPGA device and clock rate. DSP Builder
implements the hardware as VHDL with scripts that integrate with the Quartus II
software and the ModelSim simulator.
The combination of these features allows you to create a design without intimate
device knowledge, which can run on a variety of FPGA families with different
hardware architectures.
After specifying the desired clock frequency, number of channels, and other top-level
design constraints, the generated RTL is automatically pipelined to achieve timing
closure. By analyzing the system-level constraints, DSP Builder also optimizes folding
(time-division multiplexed (TDM) designs) to achieve optimum logic utilization, with
no need for manual RTL editing. |
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发表于 2011-12-13 10:21:19
我上大学时，有段时间老丢三落四，老师就这么教我的，结果就好了。
发表于 2011-12-13 10:45:52
楼主